RC Circuit of a PWM DAC

This page calculates the minimum values of R and C for a PWM-DAC at a given frequency.

Here you can see the really manageable circuit. An RC low pass filters the PWM signal so that a mostly AC-free voltage is created.

It should be noted that you could also use higher-order filters here, which would result in shorter settling times. However, these also introduce additional errors (offset, gain), higher costs, and growing board space, so a real DAC would soon be the better and cheaper choice.

Therefore, this form is limited to the first-order filter, the RC circuit.

A timer on your microcontroller usually generates the PWM signal. It counts continuously from 0 to n and the output is 1 from a certain threshold value, which then determines the duty cycle.

The final value n is constant, so that we get a fixed frequency whose duty cycle is only determined by the threshold value.

The trick with dimensioning is to select the correct time constant τ. τ is calculated from R×C. If τ is too small, the ripple of the output signal is too high; if it is too large, the settling time is unnecessarily extended.

This form always uses 1 µF for the capacitor, only the matching resistor is calculated so that the ripple is less than ½ LSB. The calculated settling time is the time required for the output signal to approach ½ LSB.

The idea behind this is that the output signal plus ripple stays within one LSB.

You can then change R and C as you wish and see the result below. The buttons Recalc R_min and Recalc C_min may be helpful here.

My prophecy: if you get no reasonable resistance values (10 kΩ..10 MΩ) for capacities between 10 nF..10 µF the circuit will render problematic or simply impractical.

Also pay attention to the tolerances of the components! The ripple is greatest with a minus tolerance, the settling time with a plus tolerance.

Therefore, it is also possible to specify a tolerance. The tolerance is the sum of the tolerances for R and C. The results are then safe values.

Design Procedure

The design process with this form is as follows:

• Enter the clock frequency of your timer and the desired resolution. The PWM frequency is calculated from this. The resolution can also be fractional, i.e. if you need 2500 counts, for example, enter 11.3 bits here (log(2500)/log(2)).

  2500 counts means your timer permanently counts from 0 to 2499. The threshold is somwhere in between, i.e. you may set 2500 different values.

  I also offer the opposite calculation, you may enter the PWM frequency and the required (minimum) clock frequency is calculated vice versa.

• Specify a tolerance for the components (sum of Tol_R and Tol_C in percent), preferably a little more.
• You will then see the minimum required time constant and a suggestion for R and C. C is initially always 1µF, only R is calculated accordingly.
• Adjust R and C to obtain a τ with the required margin and a corresponding ripple (The recalc buttons may be helpful here).
• Check the values based on the information below and adjust R or C to stay within the required limits of τ and ripple.
• Finally you will also see the necessary settling time.
• Further increasing R (or C) causes a smaller ripple but increases the settling time. Simply try it and adopt it to your needs!

Attention: even the backward calculation (Rselected - tolerance) must not lead to an impermissibly high ripple! This requires some additional math, but it is accounted for in this form. But it is the reason why R_min is larger than you might expect from the minimum τ.

Then we get a settling time of 66.54 ms. If the tolerances of R and C both happen to be positive, we still have to add them, so the worst-case settling time is around 25% higher (20% C plus 5% R), i.e. at least 84 ms. That's the only thing we can guarantee. It may be better, but it doesn't have to be.

If we specify 25% tolerance, this is automatically added to both the minimum τ and the settling time. Since an 11.83 kΩ resistor is not available for purchase, we still have to manually set 12 kΩ here to see the final settling time.

Of course, you can also use 5% capacitors and 1% resistors (a total of 6%), which results in a reduced settling time of less than 60 ms, if necessary and the additional cost is tolerable.

I would prefer the 25% if possible, as I wouldn't have to worry about whether the purchasing department had arbitrarily sourced cheaper alternatives.

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You may be wondering why you don't have to (or can't) enter a voltage anywhere, but the voltage cancels out in all equations. Only the PWM frequency and time constant determine resolution and settling time of the circuit, regardless of whether you operate it with 3.3 V, 5 V or 255 V.

Preferably use film capacitors as ceramic capacitors (e.g. X7R) also have a considerable voltage dependence of the capacitance. However, ceramic capacitors with NP0/C0G should also work well.

You will also see that you then get settling times in the range of of years! Even if this would be acceptable, it would not result in 24 bit accuracy.

In addition, there are leakage currents and temperature dependencies which, even with just hours of conversion time, can certainly have an impact.

I assume that more than 8, 10 or a maximum of 12 bits are not reasonably possible with this circuit.

Also note that each additional bit halves the PWM frequency! This quickly leads to impractical component values and long settling times. At 12 Bit, even a 24 MHz timer can only deliver 5.8 kHz PWM, which results in a settling time of almost 5 s.

In summary, I can say that a PWM DAC can be relatively accurate, is dirt cheap but has the disadvantage of considerably long settling times, which disqualifies it for many cases. In addition, its signal is not a DC value like with a commercially available DAC, but always contains a certain amount of ripple, which in many cases may not actually be a problem.

In audio applications, however, you may hear the PWM frequency ringing...

If you have rashly implemented a PWM DAC and only later realize that it is no good, the LTC2645 might be able to help you out. It practically eliminates the settling time, up to 12 Bit resolution. Otherwise, a SPI-DAC would be the better solution.

I implemented this part just for fun and curiosity (but also to see if the forward calculation works correctly), it is rarely needed in practice, but you can use it to check the performance of a given PWM DAC.

Enter the PWM frequency, R and C and the tolerance and you will see the achievable resolution (i.e. when the ripple is ≤ ½ LSB) and the settling time (down to ½ LSB).

Here, too, the resolution is calculated with a minus tolerance and the settling time with a plus tolerance so that the results are again safe values.

If you get a lower resolution than promised, you will have more than ½ LSB ripple; if you get more than the promised settling time, the value will not come within ½ LSB of the target value in this time.

You might come up with the idea of increasing R and you will quickly reach dream values. But keep an eye on the last value, the minimum necessary clock frequency (fClk)! If you do not reduce the PWM frequency accordingly, you will quickly get unrealistic values here!

It should also be noted that there is a method to significantly reduce ripple by differentiating the inverted PWM signal, as shown here.

With the values calculated above, the ripple becomes almost negligible. However, the settling time increases considerably.

You can then significantly reduce τ until the ripple rises back to ½ LSB and ultimately achieve a significantly reduced settling time.

However, this circuit relies on the resistors and capacitors being exactly the same. Even minimal deviations within the tolerances cause the ripple to increase significantly.

You would then either have to use components with tighter tolerances (which would increase costs) or you would have to select the components (which would be even more expensive). I consider this circuit theoretically interesting, but also practically almost irrelevant.

If 800 ms isn't fast enough, 100 ms probably won't be either, and you'll be forced to switch to a real DAC that can do the job at least 100,000 times faster.

With the data from my form, no dimensioning can be derived here and if you think it would help, I can only recommend that you simulate it, ideally with a Monte Carlo analysis, to see the influence of tolerances.

The inverted PWM signal is already available in many controllers, so the additional effort is limited to just one resistor and one capacitor.